JUNIPER EX2300-48P-VC EX2300 Series Ethernet Switches

EX2300-48P-VC Hardware Identity

EX2300-48P-VC is a Juniper EX2300 fixed-configuration Ethernet switch. Its verified hardware profile is 48 10/100/1000BASE-T access ports; PoE/PoE+ on all 48 access ports. The complete code carries Virtual Chassis license/order qualifier. Preserve every suffix on the quote, carton and asset record.

Port and power boundary

740 W maximum PoE/PoE+ budget. The uplink configuration is four SFP/SFP+ uplinks. Optics, optional uplink modules, cables and any separately ordered power or mounting items must be reconciled in the final bill of materials.

EX2300 architecture control

EX2300 acceptance should reflect a compact access-switch design. Record the fixed power arrangement, access-port population and the exact number of SFP/SFP+ uplinks on this model. If Virtual Chassis is planned, Juniper documents a maximum of four EX2300 members and requires SFP+ rather than SFP transceivers for VCP links. Preserve member IDs, VCP optics, Junos release and recovery behavior. Do not borrow EX3400 redundant-supply or larger-chassis assumptions.

Order-form control 1

AC power acceptance requires the supported input range, regional cord, receptacle, circuit capacity and selected supply wattage to be documented. Where redundant supplies are used, place them on the intended independent circuits and test loss of one feed. Do not substitute a DC chassis or mix supply wattage or airflow. Retain supply serials, cord type and circuit labels with commissioning evidence.

Order-form control 2

Where the PID has no explicit AFI or AFO suffix, use the Juniper model table and actual FRU labels to establish the shipped airflow. Record intake and exhaust orientation before rack placement, and reject any replacement fan or supply whose airflow differs. The absence of a suffix is not permission to mix directions or to infer the pattern from another chassis.

Order-form control 3

The VC suffix must be reconciled with the intended Virtual Chassis deployment. Record member count, VCP interfaces and optics, topology, software release, primary and backup roles, preprovisioning and split-brain recovery. Confirm what the order qualifier supplies and what remains a separate optic or cable. A standalone link-up test does not validate the VC design.

SKU-specific acceptance

For the VC-qualified PoE line, separate the Virtual Chassis entitlement decision from the PoE budget and uplink transceiver design. Assign member IDs and VCP links before racking, then reserve PoE budget for the endpoint population on this exact member. Test loss and return of one VCP while monitoring powered devices, management reachability and mastership. Keep the VC license/order evidence separate from optics, cabling and power acceptance.

Airflow match

Record rack cold aisle, intake side and exhaust side. Fan modules and power supplies must use the same airflow direction; a suffix mismatch is a receiving failure.

Junos baseline

Record the approved Junos release and hardware support evidence before staging. Preserve the initial configuration, rescue state and post-upgrade validation.

Uplink plan

Map every uplink speed, optic, breakout, LAG member and peer. Optional uplink modules and transceivers must appear as separate bill-of-material lines where required.

Capacity test

Measure representative access, uplink and control-plane load after staging. Preserve errors, drops, temperature and latency rather than accepting link-up alone.

Failure domain

Define what remains online after loss of one feed, supply, fan, uplink or VC member. Test the approved failure case and retain recovery timing.

PoE load

Build a port-by-port powered-device budget with startup draw, redundancy state and spare margin. Do not equate a PoE-capable port count with enough available watts.

Related Juniper EX records

• EX2300-48T-VC switch record
• EX2300-24T-VC switch record
• EX4300-48T-AFI-TAA switch record

Official Juniper evidence

EX2300 system overview and model table. Verify the current hardware guide, supported Junos release and lifecycle notice at the final design date.